CompactPCI Serial - The Next Generation CompactPCI

Ecosystem for CompactPCI® Serial (CPCI-S.0)

2010-10-15, A. Lenkisch u.a.

Older bus systems for embedded computers, such as VMEbus and CompactPCI®, have reached their limits. CompactPCI® PlusIO and CompactPCI® Serial are two new PICMG specifications that are expected to carry CompactPCI® technology into the future. CompactPCI® PlusIO forms the bridge to the new, wholly serial architecture known as CompactPCI® Serial (originally called "CompactPCI® Plus").
The parallel bus of CompactPCI® has been replaced by fast serial data transfer mechanisms. Both new technologies use the PCI Express®, Gigabit Ethernet, USB and Serial ATA interfaces that are commonly used in PCs. Existing solutions from the consumer market that use these transfer methods can be adapted very easily to CompactPCI® PlusIO and CompactPCI® Serial. An ordinary 2.5" or 3.5" hard disk can for example be fitted to a CompactPCI® Serial plug-in board and be linked into the system via SATA without protocol adaptation. Similarly a USB flash memory drive or a WiFi stick can be mounted on a board and linked to the processor board via the USB bus present on every slot. The possibilities are enormous and the user can benefit greatly from the ecosystem of the PC market.

It will however also still be possible to fall back on the existing CompactPCI® ecosystem. CompactPCI® Serial is a standalone specification and represents the successor to CompactPCI®. In this, only the fast serial data transfer protocols are present. To avoid an abrupt jump from CompactPCI®, however, the CompactPCI® PlusIO specification was created as a sub-specification to the CompactPCI® base specification in order to provide a soft migration path. CompactPCI® PlusIO defines a uniform pinout on the P2 connector of the 32-bit CompactPCI® system slot, on which the 4 new serial buses, PCIe®, GbE, S-ATA and USB, are defined. Thus it is possible to construct hybrid CompactPCI® / CompactPCI® Serial systems (Fig. 1). On the P1 connector the CPU addresses the parallel CompactPCI® slots in the system, while the P2 area is connected to the fast serial CompactPCI® Serial slots. System components such as slow I/O boards can thus be retained on CompactPCI®, and only special boards that require one of the new protocols or increased bandwidth must be converted to the new technology.

Fig. 1: Hybrid chassis: CPCI / CPCI Serial

The user thus already has the benefits of two existing ecosystems. A large number of board manufacturers exist for CompactPCI®. These have their place in the hybrid system. Even the countless solutions for the mass PC market can be introduced into the new system with a minimum of development outlay. In most cases this is no more than a minor design outlay plus mechanical fixing and a few data and power cables on the board.

CompactPCI® PlusIO was approved in December 2009. The CompactPCI® Serial specification is still in development and is expected to be released this year. For this reason, there can naturally not yet be a wide range of components such as already exists for CompactPCI®. However, there are already a number of processor boards available for CompactPCI® PlusIO. CompactPCI® Serial processor boards will be available shortly.

Systems and backplanes are already available for both specifications. Examples include 8-slot hybrid backplanes with 3 CompactPCI® peripheral slots, a CompactPCI® PlusIO system slot and 4 CompactPCI® Serial peripheral slots. These backplanes are available in two versions, with and without rear I/O on the CompactPCI® Serial slots. These backplanes represent the maximum configuration for hybrid systems and can thus be used for all possible applications. Backplanes with a smaller number of slots are already being planned, for example a 5-slot version. For CompactPCI® Serial there is initially the maximum configuration with 9 slots, 1 system slot and 8 peripheral slots (Fig. 2). Here again, all possible applications can be realised. There are even 4 different versions - on all of which PCIe®, USB and SATA are realised as single star. One version is also designed as a single star for Gigabit Ethernet, while the other version has full-mesh wiring in the Gigabit Ethernet area and is thus best designed for building up processor farms or clusters. Both of these versions are available either with or without rear I/O.

Fig. 2: 9-slot CPCI Serial backplane, system slot to left

Andreas Lenkisch, Principal Engineer for Backplanes, Schroff® GmbH
Christian Ganninger, Global Product Manager for Systems, Schroff® GmbH

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