Signal integrity on CompactPCI® Serial backplanes

2009-10-15, Andreas Lenkisch

In CompactPCI® Serial the earlier parallel PCI bus is replaced by the high-speed PCI Express® interface. In addition the ATA, USB and Ethernet interfaces, which are likewise based on high-speed, point-to-point connections, have been added. As a result the transfer rate has increased beyond that of the parallel bus by a factor of 300. And instead of approximately 150 networks, CompactPCI® Serial allows more than 360, of which 340 are high-speed.
So what are the problems that are currently causing a high bit error rate (BER)?
As the clock or data frequency increases, the data signal wavelength decreases in proportion to v/f (where v = signal propagation velocity in the transfer medium, f = frequency). When the wavelength of the signal becomes so short as to approach the order of magnitude of lengths of the PCB tracks and other signal path elements, reciprocal effects occur that can lead to resonance and severe distortion of the signal. While in CompactPCI® the entire circuit board was still considerably shorter than the signal wavelength, in the new configuration even a few millimetres of PCB track between two discontinuities in the signal path can be critical, as is also the length of a via (Fig. 1). At every impedance mismatch, signal energy is reflected, and this is the major problem of relatively short conductors, since the reflections are not sufficiently damped. It is thus not so much the losses associated with longer lines that lead to a high bit error rate at the receiver, but rather the reflections. Losses can in any case be relatively easily compensated (with pre-emphasis and equalisation), but this is not the case for reflections. Reflections increase noise and jitter and thus also the BER.
CompactPCI® Serial backplanes carry twice the number of signals and have less space between the connectors, which results in a high density of conductors. The signal lines are thus necessarily very close to one another, and excessive crosstalk can occur.
Crosstalk, like reflections, contributes to noise and jitter. The skill of the designer is therefore in obtaining the best compromise between conductor density and the number of layers, and generally keeping impedance discontinuities to a minimum.
The use of 3D modelling of the board elements and simulation of the entire transmission channel to determine the bit error rate is a very helpful method for designing PCBs and backplanes with a sufficiently low bit error rate at the first draft (Fig. 2).


3D model of a connector via field


Eye diagram with a sufficient opening

Andreas Lenkisch, Principal Engineer Backplanes, Schroff® GmbH, Straubenhardt, Germany

German version on ElektronikPraxis: Signalintegrität auf CompactPCI Plus Backplanes

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